Uncertainty modeling of gate delay considering multiple input switching

With the continual advancement in manufacturing technologies and the resultant process variations, delay variability is becoming increasingly significant. Statistical models have become mandatory to model the delay variability. It has also been experimentally proved that ignoring multiple input switching and approximating it by single input switching results in significant error. We propose a new gate delay model that considers the impact of both process variations and multiple input switching. The proposed model uses an orthogonal polynomial based probabilistic collocation method to construct a delay analytical equation from a circuit´s output response. The obtained analytical equation is used to evaluate the output delay distribution. Experimental results show that our approach gives a mean delay error less than 0.1% and a standard deviation error less than 2% when compared with Monte Carlo analysis.