Title :
Low power clock-synchronizer for SOC with delay line controller (DLC) in 45nm CMOS technology
Author :
Srivathsava, N.L. ; Kulkarni, Tripti
Author_Institution :
Dept. of Electron. & Commun, PES Inst. of Technol., Bangalore, India
Abstract :
Clock synchronizer is the circuit which synchronizes the clock provided to different loads (modules or functional blocks). The advancement of the VLSI has led to new field- SoC. The clock synchronizer finds its application in SoC. The clock-synchronizer in SoC has to maintain the clock skew between modules zero. This paper presents clock synchronizer architecture. This synchronizer is designed on 45nm CMOS technology, simulated using Tanner EDA tool and T-SPICE, with 2V power supply. The average power consumed is 6.688514e-002 watts.
Keywords :
CMOS integrated circuits; VLSI; synchronisation; system-on-chip; CMOS technology; DLC; SoC; T-SPICE; Tanner EDA tool; VLSI; delay line controller; low power clock-synchronizer architecture; Clocks; Partial discharges; Phase locked loops; Switches; Synchronization; System-on-a-chip; Duty Cycle to Digital Converter; Dynamic Voltage and Frequency scaling (DVFS); Phase Frequency Detector (PFD) Charge Pump (CP); Phase locked loop (PLL); System On Chip (SoC); dead lock state; delay line controller (DLC); guard band; pulse-triggered capturing circuit; variable delay line (VCDL);
Conference_Titel :
Advanced Communication Control and Computing Technologies (ICACCCT), 2012 IEEE International Conference on
Conference_Location :
Ramanathapuram
Print_ISBN :
978-1-4673-2045-0
DOI :
10.1109/ICACCCT.2012.6320749
