Increased jitter sensitivity in continuous- and discrete-time ΣΔ modulators due to finite opamp settling speed

This paper concerns the influence of finite gain-bandwidth on the clock jitter sensitivity in both continuous- and discrete-time sigma-delta (ΣΔ) A/D converters. Therefore, two different architectures are considered, a CT and a DT modulator, both with switched capacitor feedback. It is shown for the first time that the commonly assumed clock jitter insensibility of the switched-capacitor, DT architecture is tremendously disturbed, if the integrators are build with nonideal gain-bandwidth, and that the same holds true for the CT modulator with switched-capacitor feedback. Consequently, clock jitter arises to be a major concern for all ΣΔ architectures, if low bandwidth integrators are used.