A precise clock phase multiplier

The continuing demand for higher bandwidth has pushed data rates over serial communication links to ≥10 Gbit/s. Many of these I/O links use precisely spaced clock phases that are accurate to within a fraction of the bit interval. This paper presents a novel architecture for generating multiple clock phases where the position of each clock phase is precisely controlled. This accuracy is achieved by employing dedicated feedback loops which monitor and adjust the position of every clock edge until their relative phase shifts are precisely equal. A discrete time analysis of the proposed multiple loop architecture was carried out to examine its stability.