A spread spectrum clock generator for SATA-II

Author

Chen, Wei-Ta ; Hsu, Jen-Chien ; Lune, Hong-Wen ; Su, Chau-Chin

Author_Institution

Dept. of Electr. & Control Eng., Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan

fYear

2005

fDate

23-26 May 2005

Firstpage

2643

Abstract

In this paper, we proposed a spread spectrum clock generator (SSCG) for the Serial AT Attachment Generation 2 (SATA-II). We use a fractional-N PLL to accomplish the spread spectrum function. The SSCG integrates a conventional PLL, a digital 3^rd order MASH 1-1-1 delta-sigma modulator and an address generator. The SSCG generates clocks at 1.5 GHz, a 5000 ppm down spread with a triangular waveform frequency modulation of 33 kHz. The circuit has been simulated in 0.18 μm CMOS technology. The non spread spectrum clocking has a jitter of 80 ps and the peak amplitude reduction is 23.44 dBm in spread spectrum mode. The power dissipation from a 1.8 V supply is 55 mW.

Keywords

CMOS integrated circuits; circuit simulation; clocks; delta-sigma modulation; integrated circuit design; integrated circuit measurement; jitter; phase locked loops; spread spectrum communication; 0.18 micron; 1.5 GHz; 1.8 V; 33 kHz; 55 mW; SATA-II; SSCG; Serial AT Attachment Generation 2; address generator; circuit CMOS technology simulation; digital third order MASH delta-sigma modulator; fractional-N PLL; nonspread spectrum clocking jitter; peak amplitude reduction; power dissipation; power supply; spread spectrum clock generator; spread spectrum function; spread spectrum mode; triangular waveform frequency modulation; CMOS technology; Circuit simulation; Clocks; Delta modulation; Digital modulation; Frequency modulation; Jitter; Multi-stage noise shaping; Phase locked loops; Spread spectrum communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465169

Filename

1465169