The implementation of modulator using FPGA technology for W-CDMA WLL

Author

Park, Hyeong Sook ; Sohn, Dyung Yeol ; Kim, Dae He

Author_Institution

Mobile Commun. Div., Electron. & Telecommun. Res. Inst., South Korea

fYear

1997

fDate

7-10 Sep 1997

Firstpage

79

Lastpage

83

Abstract

This paper describes the design and implementation of the modulator in subscriber unit for wideband code division multiple access (CDMA) wireless local loop (WLL) testbed with 5 MHz bandwidth using Field Programmable Gate Array (FPGA) technology. The modulator presented in this paper provides two main functions: it carries out the complete digital modulation process for the reverse link and deinterleaves the forward-link symbols received from the symbol combiner of the demodulating unit. Also, the spectral degradation due to quantization error of filter coefficients and truncation of filter output is simulated. Filter output signals obtained from this implemented modulator are also included

Keywords

code division multiple access; field programmable gate arrays; modulators; quadrature phase shift keying; quantisation (signal); radio links; subscriber loops; 5 MHz; FPGA technology; W-CDMA WLL; deinterleaving; digital modulation process; field programmable gate array; filter coefficients; filter output signals; forward-link symbols; quantization error; spectral degradation; subscriber unit; symbol combiner; wideband code division multiple access; wireless local loop; Bandwidth; Degradation; Digital modulation; Field programmable gate arrays; Filters; Modulation coding; Multiaccess communication; Quantization; Testing; Wideband;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International

Conference_Location

Portland, OR

ISSN

1063-0988

Print_ISBN

0-7803-4283-6

Type

conf

DOI

10.1109/ASIC.1997.616982

Filename

616982