Title :
VLSI implementation of STM-1 Framer and De-Framer
Author :
Sundeep, B.A. ; Anand, Tejasvi ; Yellampalli, Siva S.
Author_Institution :
VTU Extn Centre, UTL Technol. Ltd., Bangalore, India
Abstract :
In this paper we present the VLSI implementation of STM-1 Framer and De-Framer. This paper mainly focuses on multiplexing digital data, transmitting and receiving the STM-1 frame. The design is implemented using Verilog HDL, simulated on Modelsim and Synthesized on Xilinx ISE 13.2. For power analysis and area calculation, the designed framer and de-framer are analyzed using Cadence version 6.1.5. The designed framer can be used for generation and analysis of STM-1 frame that has a data rate of 155.52Mbps.
Keywords :
VLSI; data handling; hardware description languages; microprocessor chips; power aware computing; Cadence version 6.1.5; De-Framer; STM-1 Framer; VLSI implementation; Xilinx ISE 13.2; area calculation; multiplexing digital data; power analysis; verilog HDL; Clocks; Containers; Multiplexing; Payloads; Signal generators; Synchronous digital hierarchy; Very large scale integration; BIP; Descrambler; POH; PRBS; SOH; STM-1 frame; Scrambler;
Conference_Titel :
Advanced Communication Control and Computing Technologies (ICACCCT), 2012 IEEE International Conference on
Conference_Location :
Ramanathapuram
Print_ISBN :
978-1-4673-2045-0
DOI :
10.1109/ICACCCT.2012.6320778
