Title :
An Efficient FPGA Implementation of the Advanced Encryption Standard Algorithm
Author :
Trang Hoang ; Van Loi Nguyen
Author_Institution :
Univ. of Technol., Ho Chi Minh City, Vietnam
fDate :
Feb. 27 2012-March 1 2012
Abstract :
A proposed FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in this paper. This implementation is compared with other works to show the efficiency. The design uses an iterative looping approach with block and key size of 128 bits, lookup table implementation of S-box. This gives low complexity architecture and easily achieves low latency as well as high throughput. Simulation results, performance results are presented and compared with previous reported designs.
Keywords :
cryptography; field programmable gate arrays; table lookup; FPGA implementation; S-box; advanced encryption standard algorithm; iterative looping approach; lookup table; low complexity architecture; word length 128 bit; Algorithm design and analysis; Clocks; Encryption; Field programmable gate arrays; Signal processing algorithms; Throughput;
Conference_Titel :
Computing and Communication Technologies, Research, Innovation, and Vision for the Future (RIVF), 2012 IEEE RIVF International Conference on
Conference_Location :
Ho Chi Minh City
Print_ISBN :
978-1-4673-0307-1
DOI :
10.1109/rivf.2012.6169845
