Effective capacitance for gate delay with RC loads

In deep submicron designs, the resistance of interconnect plays a dominant role on the timing behavior of logic gates. The concept of effective capacitance C_eff is usually used to calculate the gate delay for interconnect loads. In this paper, a new method to derive the expression C_eff is presented, and the accuracy of the expression is discussed. In our approach, the output waveform is assumed as linear. Thus, the expression of effective capacitance is simple and efficient. Moreover, the result of effective capacitance is insensitive to output wave shape because C_eff is determined by the curve area. Therefore, it is appropriate for various output waveforms of a CMOS gate with RC loads. Experimental results show it is in agreement with the Spice simulation.