Title :
A novel architecture for binary comparison using time division de-multiplexing technique
Author_Institution :
Deptt. of Electrical Engg., National Institute of Technology Silchar, India
Abstract :
This paper proposes the design of a novel comparator which uses a Time Division De-multiplexing (TDD) unit for binary comparison. The function of the TDD unit is to generate clock pulses in such a pattern that they can be used to trigger one of the two D flip-flops in the proposed comparator architecture, depending on - which of the two numbers being compared is greater. The proposed comparator is simulated using Verilog HDL programming in Xilinx ISE 8.2i platform and its functionality is verified. An application-specific advantage of this architecture is proposed in this paper.
Keywords :
circuit simulation; clocks; comparators (circuits); computer architecture; digital arithmetic; flip-flops; hardware description languages; logic design; pulse generators; time division multiplexing; trigger circuits; D flip-flop trigger; TDD unit; Verilog HDL programming; Xilinx ISE 8.2i platform; binary comparison; clock pulse generation; comparator architecture; comparator design; comparator simulation; time division de-multiplexing technique; Barium; Clocks; Computer architecture; Logic gates; Multiplexing; World Wide Web; D flip-flop; parallel architecture; pulses; serial architecture; synchronised; time division de-multiplexing; up-counter;
Conference_Titel :
Advanced Communication Control and Computing Technologies (ICACCCT), 2012 IEEE International Conference on
Conference_Location :
Ramanathapuram
Print_ISBN :
978-1-4673-2045-0
DOI :
10.1109/ICACCCT.2012.6320826
