Boundary scan with parallel test access mechanism

Author

Ke, Han ; Zhongliang, Deng ; Jianming, Huang

Author_Institution

Sch. of Electron. Eng., Beijing Univ. of Posts & Telecommun., Beijing, China

fYear

2009

fDate

16-19 Aug. 2009

Firstpage

25659

Lastpage

26755

Abstract

Along with the more complicated integrated circuit and emergence of IP based systems on a chip (SoC), new challenges are encountered in the designing for testability (DFT). The test power dissipation is one of the critical factors which should be considered carefully when designing the SoC for testability. In this paper, a parallel test access mechanism using boundary scan technique is proposed with its test controller. The test action mechanism (TAM) and the controller can be selected flexible for the test cost and the power dissipation.

Keywords

boundary scan testing; design for testability; integrated circuit testing; system-on-chip; SoC design; boundary scan technique; designing for testability; integrated circuit testing; parallel test access mechanism; system on chip; test controller; test power dissipation; Circuit testing; Design for testability; Electronic equipment testing; Integrated circuit testing; Partial discharges; Power dissipation; Semiconductor device measurement; Shift registers; System testing; System-on-a-chip; Designing for testability (DFT); Joint Test Action Group (JTAG); boundary scan technique; test power dissipation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Measurement & Instruments, 2009. ICEMI '09. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-3863-1

Electronic_ISBN

978-1-4244-3864-8

Type

conf

DOI

10.1109/ICEMI.2009.5274683

Filename

5274683