Title :
Layout verification to improve ESD/latchup immunity of scaled-down CMOS cell libraries
Author :
Ker, Ming-Dou ; Hsiao, Sue-Mei ; Lin, Jiann-Horng
Author_Institution :
Ind. Technol. Res. Inst., Hsinchu, Taiwan
Abstract :
Layout verification has been proposed to improve the ESD (Electrostatic Discharge) and latchup immunity of scaled-down CMOS cell libraries. By using the DRC (design rules check) and ERC (electrical rules check), the ESD/latchup sensitive layout can be found. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the cells, the ESD and latchup reliability of CMOS IC´s assembled by the layout-verified cell libraries can be significantly improved
Keywords :
CMOS logic circuits; cellular arrays; circuit layout CAD; electrostatic discharge; integrated circuit layout; integrated circuit reliability; logic CAD; ESD; design rules check; electrical rules check; latchup immunity; layout area; layout verification; reliability; scaled-down CMOS cell libraries; standard cells; CMOS technology; Circuit testing; Electrostatic discharge; Internal stresses; Libraries; Pins; System testing; Variable structure systems; Very large scale integration; Voltage;
Conference_Titel :
ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International
Conference_Location :
Portland, OR
Print_ISBN :
0-7803-4283-6
DOI :
10.1109/ASIC.1997.616991
