DocumentCode :
3545992
Title :
A robust CMOS logic technique for building high frequency circuits with efficient pipelining
Author :
Gayles, Eric ; Acken, Kevin ; Owens, Robert M. ; Irwin, Mary Jane
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
fYear :
1997
fDate :
7-10 Sep 1997
Firstpage :
168
Lastpage :
172
Abstract :
Current fine grain pipelining techniques, such as True Single-Phase, allow for high frequency circuit design at the cost of significant latency per operation. On the other hand, low latency designs require complex circuitry within pipeline stages, which is not feasible when designing high clock frequency systems. In this paper, we propose a novel CMOS circuit technique that allows both high frequency circuits and low cycle latency per operation. Our technique differs from other logic families that have attempted to provide the same advantages by being more robust in the presence of process variations and signal coupling. To show the feasibility of our circuit technique, we also present a 64 bit carry-lookahead adder using this circuit technique that is capable of calculating a 64 bit add every 2.0 nanoseconds
Keywords :
CMOS logic circuits; adders; logic design; pipeline processing; 2.0 ns; 64 bit; CMOS logic; carry-lookahead adder; fine grain pipelining; high frequency circuit design; latency; Buildings; CMOS logic circuits; CMOS technology; Circuit synthesis; Clocks; Costs; Delay; Frequency; Pipeline processing; Robustness;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International
Conference_Location :
Portland, OR
ISSN :
1063-0988
Print_ISBN :
0-7803-4283-6
Type :
conf
DOI :
10.1109/ASIC.1997.616999
Filename :
616999
Link To Document :
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