Efficient DSP architecture for high-quality audio algorithms

Author

Yoon, Suk Hyun ; Moon, Jong Ha ; Sunwoo, Myung Hoon

Author_Institution

Sch. of Electr. & Comput. Eng., Ajou Univ., Suwon, South Korea

fYear

2005

fDate

23-26 May 2005

Firstpage

2947

Abstract

This paper presents specialized DSP instructions and their hardware architecture for high-quality audio algorithms, such as the MPEG-2/4 advanced audio coding (AAC), Dolby AC-3, MPEG-2 backward compatible (BC), etc. The proposed architecture is specially designed and optimized for the IMDCT (inverse modified discrete cosine transform), and Huffman decoding in the AAC decoding algorithm. Performance comparisons show a significant improvement compared with TMS320C62× and ASDSP21060 for the IMDCT computation. Furthermore, the dedicated Huffman accelerator performs the decoding process in only one cycle. The proposed DPU (data processing unit) consists of 107,860 gates and achieves 150 MIPS.

Keywords

Huffman codes; audio coding; digital signal processing chips; discrete cosine transforms; 150 MIPS; AAC; DPU; DSP architecture; DSP instructions; Dolby AC-3; Huffman accelerator; Huffman decoding; IMDCT; MEPEG-2/4; MPEG-2 backward compatible; advanced audio coding; data processing unit; high-quality audio algorithms; inverse modified discrete cosine transform; Algorithm design and analysis; Audio coding; Computer architecture; Data processing; Decoding; Design optimization; Digital signal processing; Discrete cosine transforms; Hardware; Variable speed drives;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465245

Filename

1465245