Title :
Optimal complex operator mapping
Author :
Savoj, Hamid ; Wang, Duen-Jeng ; Hoang, David ; Chi-Lai Hiang
Abstract :
This paper presents a RTL synthesis flow that considers area minimization in mapping to complex cells from a technology library. A mapping decision is made by examining the complete design, If a complex cell in the middle of a design has many redundancies because of the boundary conditions (inputs or outputs of the complex cell are somwehow related) the Boolean equations for the complex cell are simplified and the cell is implemented from single-output Boolean gates. Otherwise, the complex cell from the library is retained. This approach not only achieves smaller design but also improves the testability of the overall design
Keywords :
Boolean functions; combinational circuits; design for testability; logic CAD; logic gates; minimisation of switching nets; redundancy; Boolean equations; RTL synthesis flow; area minimization; boundary conditions; complex operator mapping; mapping decision; redundancies; single-output Boolean gates; technology library; testability; Boundary conditions; Design optimization; Equations; Libraries; Logic design; Process design; Routing; Synthesizers; Testing; Timing;
Conference_Titel :
ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International
Conference_Location :
Portland, OR
Print_ISBN :
0-7803-4283-6
DOI :
10.1109/ASIC.1997.617008
