DocumentCode :
3546203
Title :
A robust 3rd order low-distortion multi-bit sigma-delta modulator with reduced number of op-amps for WCDMA
Author :
Chio, Kin-Sang ; U, Seng-Pan ; Martins, R.P.
Author_Institution :
Analog & Mixed-Signal VLSI Lab., Univ. of Macau, Macao, China
fYear :
2005
fDate :
23-26 May 2005
Firstpage :
3099
Abstract :
This paper describes a novel single-loop multi-bit (3 bits) sigma-delta modulator (SDM) with reduced number of operational amplifiers for wideband WCDMA. Such an architecture is based on a simplified analog structure that not only features low distortion but also provides an aggressive and significantly enlarged noise shaping bandwidth with low oversampling ratio (OSR). With a sampling frequency of 39 MHz and an OSR of 10 the proposed circuit can achieve 74 dB SFDR.
Keywords :
3G mobile communication; distortion; sigma-delta modulation; signal sampling; 39 MHz; WCDMA; low-distortion sigma-delta modulator; multi-bit sigma-delta modulator; noise shaping bandwidth; oversampling ratio; robust third order sigma-delta modulator; single-loop sigma-delta modulator; Bandwidth; Broadband amplifiers; Circuits; Delta-sigma modulation; Frequency; Multiaccess communication; Noise robustness; Noise shaping; Operational amplifiers; Sampling methods;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
Type :
conf
DOI :
10.1109/ISCAS.2005.1465283
Filename :
1465283
Link To Document :
بازگشت