A low-voltage low-distortion MOS sampling switch

Author

Yang, Chun-Yueh ; Hung, Chung-Chih

Author_Institution

Dept. of Commun. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2005

fDate

23-26 May 2005

Firstpage

3131

Abstract

In order to reduce distortion due to variation of the gate overdrive and the threshold voltage, a novel low-voltage constant-resistance sampling switch is proposed. The technique to reduce nonlinearity can be used in a high resolution sample-and-hold circuit. TSMC 0.18 μm standard CMOS technology is used. Results indicate that much lower total harmonic distortion (THD) is achieved by the proposed circuit. The low THD meets the requirements in the application of low-voltage low-distortion switched-capacitor circuits.

Keywords

CMOS analogue integrated circuits; field effect transistor switches; harmonic distortion; integrated circuit design; low-power electronics; network analysis; sample and hold circuits; switched capacitor networks; 0.18 micron; CMOS technology; constant-resistance sampling switch; gate overdrive; high resolution sample-and-hold circuit; low-distortion MOS sampling switch; low-voltage MOS sampling switch; switched-capacitor circuits; threshold voltage; total harmonic distortion; CMOS technology; Capacitors; Communication switching; Immune system; Low voltage; Packaging; Sampling methods; Switches; Switching circuits; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465291

Filename

1465291