Title :
FPGA-based FIR filters using digit-serial arithmetic
Author :
Lee, Hanho ; Sobelman, Gerald E.
Author_Institution :
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
Abstract :
This paper describes the use of digit-serial arithmetic for compact and efficient implementations of real-time DSP applications on field programmable gate arrays (FPGAs). As an example, the implementation of a digit-serial 5-tap FIR filter on a Xilinx XC4010 FPGA is considered. An analysis of the performance comparison of several FIR filters is described. The results show that digit-serial designs with a digit-size of 2 bits have about 17% smaller area-time product than those of a bit-serial implementations
Keywords :
FIR filters; digital arithmetic; field programmable gate arrays; real-time systems; FPGA-based FIR filters; Xilinx XC4010 FPGA; area-time product; digit-serial arithmetic; digit-size; real-time DSP applications; Arithmetic; Digital filters; Digital signal processing; Field programmable gate arrays; Finite impulse response filter; Low pass filters; Nonlinear filters; Routing; Signal processing; Throughput;
Conference_Titel :
ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International
Conference_Location :
Portland, OR
Print_ISBN :
0-7803-4283-6
DOI :
10.1109/ASIC.1997.617010
