A threshold-based algorithm and VLSI architecture of a K-best lattice decoder for MIMO systems

Lattice decoding algorithms have been shown to have the similar performance as the optimal maximum likelihood decoder for MIMO wireless systems. To reduce the high complexity of the lattice decoding algorithm and to achieve a regular fixed throughput, a K-best algorithm and the corresponding VLSI architectures have been proposed for the practical implementation of the lattice decoding algorithm. We propose a threshold-based K-best algorithm that offers a significant reduction in computation, and thus energy consumption, while still maintaining performance. The method is based on the efficient pruning of the candidates in each dimension of the search tree. At the same time, the throughputs of different VLSI implementations are studied and a high-throughput VLSI architecture is proposed. We show that by properly scheduling the hardware, optimal throughput can be achieved. Experimental results show that more than 40% of the computation can be reduced when the threshold-based K-best algorithm is used, compared with the conventional K-best algorithm. Also, a VLSI implementation based on 0.25 μm technology that can achieve a throughput of over 50 Mb/s is presented.