Chip layer assignment method for analytical placement of 3D ICs

Chip layer assignment is a key step in analytical placement of 3D ICs. Analytical placement should face the conversion from 3D continuous space in z-direction to several connected 2D chip layer spaces by layer assignment. However, layer assignment may destroy the previous optimal solution in 3D continuous space. To smooth the transition from an optimal 3D placement to a legalized, layer-assigned placement, this paper proposes a layer assignment method using the minimum cost flow, which protects solution space and inherits optimal wirelength at most. We embody this layer assignment method in a multilevel non-linear placement of 3D ICs that minimizes a weighted sum of total wirelength and TSVs number subject to area density constraints. Compared to the recently published 3D placement method [2] [7], this placement algorithm can achieve better wirelength results.