Application specific instruction-set processor generation for video processing based on loop optimization

Until recently, application specific instruction-set processor (ASIP) design was very costly and complex. Now, ASIP circuits are much easier to develop with technologies like Tensilica and Altera configurable processors that provide tools enabling effective generation of RTL (register transfer level) code for ASIPs. On the other hand, the design of effective ASIPs is still time-consuming, because existing methodologies largely rely on designers´ knowledge for design space exploration. The paper describes a methodology to help design ASIPs. An iterative profiling-driven method based on detection and acceleration of application bottlenecks with specialized instructions is proposed. This method is applied to the design of an ASIP adapted for a video processing algorithm - the Wiener filter. The acceleration reached with our method on this application is very significant, with a speedup factor larger than 10 over optimized software code.