Incremental timing optimization for automatic layout generation

This paper presents a method to improve the timing performance of combinational circuits tailored to an automatic layout generation strategy. Using a transistor sizing method, delay improvements are achieved by changing the size of gates that belong to the longest sensitizable paths. An incremental technique is used to accelerate the false path-aware timing analysis and to perform the selection of gates for sizing. The proposed transistor sizing algorithm performs discrete sizing according to the performance constraints and therefore can be applied to row-based layouts by using the folding technique. The obtained results show that the proposed method is able to optimize automatically generated circuits with smaller area penalties than currently most used sizing methods, which are based on topological timing analysis.