Title :
Performance analysis by topology indexed lookup tables
Author :
Agarwal, Patrika ; Vidyarthi, Arvind ; Madden, Patrick H.
Abstract :
Accurate analysis of VLSI interconnects is essential to the performance-driven synthesis and layout of integrated circuits. Existing techniques are based on either simulation, analytic formulas, or small-scale table lookup. There are tradeoffs in compute time and accuracy. In this paper, we present an effective approach which captures the accuracy of SPICE while remaining close to Elmore delay in terms of computational overhead. Our method is based on topology indexed lookup tables (TILT), and uses a extremely large database of precomputed values.
Keywords :
VLSI; integrated circuit interconnections; integrated circuit layout; network topology; table lookup; VLSI interconnects; accuracy; computational overhead; integrated circuit layout; performance analysis; performance-driven synthesis; precomputed value database; topology indexed lookup tables; Analytical models; Circuit simulation; Circuit topology; Computational modeling; Integrated circuit interconnections; Integrated circuit layout; Integrated circuit synthesis; Performance analysis; Table lookup; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1465403
