Optimized design of source coupled logic gates in GaAs HEMT technology

Author

Palumbo, Gaetano ; Tommasino, Pasquale ; Trifiletti, Alessandro

Author_Institution

Dipt. Elettrico, Elettronico e Sistemistico, Universita di Catania, Italy

fYear

2005

fDate

23-26 May 2005

Firstpage

3583

Abstract

A simple model for the propagation delay of source coupled logic gates composed of a differential pair and a common drain output buffer in III-V HEMT technology is proposed. The propagation delay model has been used to develop a design strategy that permits pencil-and-paper design of the gates, accounting for power-delay trade-off. The methodology has been applied to a charge-control high-frequency model of the HEMT, but is general-purpose and applicable also to different models. In the present case, percentage errors lower than 15 % have been found in propagation delay evaluation.

Keywords

HEMT integrated circuits; III-V semiconductors; buffer circuits; circuit optimisation; gallium arsenide; logic design; logic gates; optical communication; GaAs; GaAs HEMT technology; III-V HEMT technology; charge-control high-frequency model; common drain output buffer; differential pair; optimized design; pencil-and-paper design; power-delay trade-off; propagation delay; source coupled logic gates; CMOS logic circuits; Cutoff frequency; Design optimization; Gallium arsenide; HEMTs; III-V semiconductor materials; Logic design; Logic gates; Power system modeling; Propagation delay;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465404

Filename

1465404