DocumentCode :
3546706
Title :
Hardware friendly vector quantization algorithm
Author :
Matsubara, Shigeki ; Hikawa, Hiroomi
Author_Institution :
Dept. of Comput. Sci. & Intelligent Syst., Oita Univ., Japan
fYear :
2005
fDate :
23-26 May 2005
Firstpage :
3623
Abstract :
This paper proposes a new vector quantization algorithm that can be directly implemented by hardware and its performance is discussed. The algorithm is based on the assumption that most of the vector elements in the same class fall within a certain range. The proposed algorithm provides very fast vector quantization with a dedicated hardware. VHDL simulations with real world data verify the feasibility of the system followed by the circuit size and speed evaluation. Results show that the proposed system has higher performance than those of K-nearest-neighbor method or neural network approach.
Keywords :
hardware description languages; pattern classification; vector quantisation; VHDL simulations; hardware friendly vector quantization; performance; vector elements; Circuit simulation; Clustering algorithms; Computer science; Hardware; Intelligent systems; Neural networks; Prototypes; Testing; Vector quantization; Virtual colonoscopy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
Type :
conf
DOI :
10.1109/ISCAS.2005.1465414
Filename :
1465414
Link To Document :
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