A compact distance cell for analog classifiers

A parallel classifier contains a two dimensional array of distance cells computing the distance between two vector entries. Considering the silicon area consumption of such a classifier, the area and the modularity of the distance cell becomes crucial. A new single-ended distance cell that consists of six MOS transistors and one capacitor is proposed. The cell uses dynamic template storage and exploits I_DD - V_in current transfer characteristic of a simple CMOS inverter. Obviously, this approach increases the area efficiency and the speed of the cell. The cell occupies 15×15 μm² in standard 0.35 μm 5V CMOS process so that the area density offered is 4444 cells per square mm. This paper presents the description and analysis of the cell as well as its design and performance considerations.