Performance analysis of high-speed MOS transistors with different layout styles

Author

López, P. ; Oberst, M. ; Neubauer, H. ; Hauer, J. ; Cabello, D.

Author_Institution

Fraunhofer Inst. fuer Integrierte Schaltungen, Erlangen, Germany

fYear

2005

fDate

23-26 May 2005

Firstpage

3688

Abstract

Several layout schemes for MOS transistors have been investigated and compared in terms of speed and layout area. Among them, the so-called closed, donut or doughnut transistors have been characterized, obtaining an analytical expression for the calculation of the equivalent W/L ratio for a general n-side regular polygonal-shape. The comparisons show that with quasi-minimum dimension transistors and L=0.35 μm, reductions of up to 81% on the drain area can be achieved with an increase of only a 10% on the total layout area for given W and L. An application improving the switching speed of an output multiplexer is shown.

Keywords

MOSFET; UHF field effect transistors; multiplexing equipment; 0.35 micron; MOS transistor layout style; closed transistors; donut transistors; doughnut transistors; drain area; equivalent W/L ratio; general n-side regular polygonal-shape; high-speed MOS transistors; layout area; output multiplexer; performance analysis; quasi-minimum dimension transistors; switching speed; Circuit topology; Computer science; Energy consumption; MOSFETs; Multiplexing; Parasitic capacitance; Performance analysis; Power supplies; Shape; Signal resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465430

Filename

1465430