ESD protection for CMOS ASIC in noisy environments with high-current low-voltage triggering SCR devices

Author

Ker, Ming-Dou

Author_Institution

VLSI Design Div., Comput. & Commun. Res. Lab., Taiwan, China

fYear

1997

fDate

7-10 Sep 1997

Firstpage

283

Lastpage

286

Abstract

A practical solution has been proposed to safely apply the LVTSCR (low-voltage-trigger SCR) device for output ESD (electrostatic discharge) protection in the advanced submicron CMOS ASIC´s without being accidentally triggered on in the noisy operating environments. By increasing the trigger current of the LVTSCR device up to 200 mA, a noise margin greater than VDD+12V (VSS-12V) against the accidental triggering due to the overshooting (undershooting) noise pulses has been practically confirmed by the experimental results. Due to remaining a lower trigger voltage, this solution can still provide effective ESD protection for output transistors but only occupies a small layout area

Keywords

CMOS integrated circuits; MOS-controlled thyristors; application specific integrated circuits; electrostatic discharge; integrated circuit noise; integrated circuit reliability; protection; 12 V; 200 mA; CMOS ASIC protection; ESD protection; LV triggering SCR devices; accidental triggering prevention; advanced submicron ASICs; electrostatic discharge protection; high-current triggering SCR devices; noise margin; noisy environments; overshooting noise pulses; small layout area; trigger current; undershooting noise pulses; Application specific integrated circuits; CMOS technology; Diodes; Electrostatic discharge; Integrated circuit noise; Pins; Protection; Thyristors; Voltage; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International

Conference_Location

Portland, OR

ISSN

1063-0988

Print_ISBN

0-7803-4283-6

Type

conf

DOI

10.1109/ASIC.1997.617022

Filename

617022