Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC´s with substrate-triggering technique

Author

Ker, Ming-Dou ; Chen, Tung-Yang ; Wu, Chung-Yu

Author_Institution

VLSI Design Div., Comput.. & Commun. Res. Lab., Taiwan, China

fYear

1997

fDate

7-10 Sep 1997

Firstpage

287

Lastpage

290

Abstract

Four new device structures for power-rail ESD clamp circuits by using the substrate-triggering technique are investigated in submicron CMOS technology to improve ESD level of the protection device within a smaller silicon area. Experimental results in a 0.6-μm CMOS process have verified that the ESD clamp circuit with the double-BJT structure can provide 200% higher ESD robustness in per unit layout area as comparing to the previous design with the NMOS device

Keywords

CMOS integrated circuits; application specific integrated circuits; electrostatic discharge; integrated circuit design; protection; reference circuits; 0.6 micron; CMOS ASIC power rails; ESD clamp circuits; cost-efficient clamp circuits; double-BJT structure; layout area; power-rail ESD clamp circuits; submicron CMOS technology; substrate-triggering technique; CMOS process; CMOS technology; Circuits; Clamps; Electrostatic discharge; MOS devices; Protection; Rails; Robustness; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International

Conference_Location

Portland, OR

ISSN

1063-0988

Print_ISBN

0-7803-4283-6

Type

conf

DOI

10.1109/ASIC.1997.617023

Filename

617023