ASIC design of fast IP-lookup for next generation IP router

Author

Chu, Yuan-Sun ; Lin, Po-Feng ; Lin, Jia-Huang ; Su, Hui-Kai ; Chen, Ming-Jen

Author_Institution

Dept. of Electr. Eng., Nat. Chung Cheng Univ., Taiwan

fYear

2005

fDate

23-26 May 2005

Firstpage

3825

Abstract

One of the prime designs for the next generation IP routers is the IP-lookup mechanism. The IP lookup has become a major performance bottleneck for the routers. In this paper, we propose a complete hardware architecture which includes searching, updating, inserting, and deleting functions. A simple hash hardware design is used to reduce the lookup time, and a CAM is also used to solve the collision problems effectively. The ASIC includes search unit, memory controller, 1M-byte cache and 3.18 Kbytes CAM for a 32000 entries routing table. The searching, updating and deleting functions only need 1 cycle and it is 96.88% to chance to hit the correct next hop in the first cycle.

Keywords

Internet; application specific integrated circuits; cache storage; performance evaluation; routing protocols; ASIC design; CAM; cache; collision problems; deleting functions; fast IP-lookup; hardware architecture; hash hardware design; inserting; memory controller; next generation IP router; performance bottleneck; search unit; searching; updating; Application specific integrated circuits; CADCAM; Computer aided manufacturing; Computer networks; Hardware; Internet; Laboratories; Next generation networking; Protocols; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465464

Filename

1465464