DocumentCode :
3546883
Title :
A low power and high speed level shifter with delay circuits
Author :
Jia Yaoyao ; Zhang Leiming ; Chen Yiwen ; Fang Jian ; Zhang Bo
Author_Institution :
Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Volume :
2
fYear :
2013
fDate :
15-17 Nov. 2013
Firstpage :
378
Lastpage :
381
Abstract :
A level shifter with low power and high speed characteristics is proposed, which is simulated in the 0.18μm standard CMOS process. The proposed level shifter minimizes the contention problem between the pull-up PMOS transistors and pull-down NMOS transistors by using delay circuits. Compared with the conventional level shifter, the simulation results show that the proposed level shifter can achieve about 42.8% power reduction, 6.7% falling time of output level signal saving and 20.0% high-to-low propagation delay speed-up for the output load capacitance in the range of 0.2pF to 2pF when converting 1.8V to 3.3V. Besides, the proposed level shifter has about 38.4% improvement in the overall performance. Hence, the proposed level shifter is suited for low power, high speed applications.
Keywords :
CMOS integrated circuits; MOSFET circuits; delay circuits; high-speed integrated circuits; low-power electronics; CMOS; capacitance 0.2 pF to 2 pF; delay circuits; high speed level shifter; high-to-low propagation delay; low power level shifter; output level signal saving; output load capacitance; power reduction; pull-down NMOS transistors; pull-up PMOS transistors; size 0.18 mum; voltage 1.8 V to 3.3 V; Capacitance; Delays; Digital audio players; MOSFET; Power demand; Propagation delay; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, Circuits and Systems (ICCCAS), 2013 International Conference on
Conference_Location :
Chengdu
Print_ISBN :
978-1-4799-3050-0
Type :
conf
DOI :
10.1109/ICCCAS.2013.6765361
Filename :
6765361
Link To Document :
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