A study on an ASIC design technique for digital protective relays

Author

Seo, Jong-Wan ; Shin, Myong-Chul

Author_Institution

Sch. of Inf. & Commun. Eng., Sungkyunkwan Univ., Suwon, South Korea

fYear

2005

fDate

23-26 May 2005

Firstpage

3910

Abstract

This research presents core-based VLSI design for digital protective relays based on the generalized CORDIC processor. It has high-speed processing capability which is fully sufficient for parallel 12-channel sources at high sampling rate (256 samples per cycle). Required hardware can be quite reasonable in most ASIC technologies. Relaying accuracy is remarkably guaranteed through hardware exponentiation. It also provides re-programmability as in typical instruction set architectures for appropriate parameterization. The entire design was successfully built by 0.35 μm CMOS technology with a the size of 5mm × 5mm.

Keywords

CMOS integrated circuits; VLSI; digital arithmetic; instruction sets; power system protection; power system relaying; sampling methods; signal processing; system-on-chip; 0.35 micron; ASIC design technique; CMOS technology; core-based VLSI design; digital protective relays; generalized CORDIC processor; hardware exponentiation; instruction set architectures; re-programmability; sampling rate; Active filters; Application specific integrated circuits; Digital filters; Digital relays; Power harmonic filters; Power system protection; Power system relaying; Power system reliability; Protective relaying; Sampling methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465485

Filename

1465485