Nonlinear parameterized model order reduction method for synthesis and optimization of VLSI circuits

A parameterized model order reduction technique for nonlinear VLSI circuit system is presented in this paper, which combines the Proper Orthogonal Decomposition (POD) with the interpolation method and hence overcomes the inefficiency of POD in representing parameterized nonlinear functions. In order to capture the accuracy of the parameterized reduced model over a large range of parameter values, a training scheme is proposed to automatically select the training parameter points by the greedy sampling method. Results show that the accuracy and efficacy are improved in the proposed nonlinear parameterized reduction method.