Hyperblock formation: a power/energy perspective for high performance VLIW architectures

Architectures based on very long instruction word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness of these processors depends on the ability of compilers to provide sufficient instruction-level parallelism (ILP) in program codes. The main factor limiting the possibility of obtaining high ILP levels is the presence of conditional branches, which prevent a VLIW compiler from scheduling instructions belonging to different paths in parallel. Hyperblock formation is the main compiling technique to solve this limit affecting ELP, transforming the code in such a way as to eliminate conditional branches. The paper presents an analysis of the effect of this technique, not only from the well-known perspective of performance gain but from that of power dissipation and energy consumption. The effect of hyperblock formation on these magnitudes is presented for a set of typical embedded multimedia applications, introducing the non-trivial problems this aggressive ILP technique causes in the increasingly widespread scenario of multiobjective performance, energy and power optimization.