DocumentCode
3547156
Title
AHDL models to detect verification problems early in the design process
Author
Barby, J.A. ; Shen, H.
Author_Institution
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
fYear
1997
fDate
7-10 Sep 1997
Firstpage
339
Lastpage
342
Abstract
A suite of AHDL models has been developed to enhance the traditional simulation verification of an IC design before it goes to fabrication. A typical IC hardware verification unit is analyzed identifying a minimum subset of simulation models along with their specifications. Proof of concept models were written and tested on a simple IC design to illustrate their usefulness
Keywords
circuit analysis computing; digital simulation; hardware description languages; integrated circuit design; integrated circuit modelling; AHDL models; IC design; design process; hardware verification unit; proof of concept models; simulation models; simulation verification; verification problems; Circuit simulation; Hardware; Integrated circuit modeling; Integrated circuit testing; Logic; Pins; Process design; Semiconductor device modeling; Silicon; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International
Conference_Location
Portland, OR
ISSN
1063-0988
Print_ISBN
0-7803-4283-6
Type
conf
DOI
10.1109/ASIC.1997.617033
Filename
617033
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