Title :
A practical BIST circuit for analog portion in deep sub-micron CMOS system LSI
Author :
Komuro, Takanori ; Hayasaka, Naoto ; Kobayashi, Haruo ; Sakayori, Hiroshi
Author_Institution :
Agilent Technol. Int. Japan, Ltd., Tokyo, Japan
Abstract :
Nowadays the production testing of the analog portion on SoC (system on chip) devices heavily depends on LSI tester capability. However this approach is expensive and will become harder in near future. This paper proposes a new approach for the analog portion testing, which can meet requirements for high-speed and high-accuracy testing simultaneously with reasonable cost. The key concept of the new method is cooperation of an LSI tester and some circuitry built in a target SoC device. We explain the operation principle of the proposed method, and show the effectiveness of the proposed method through simulation.
Keywords :
CMOS integrated circuits; built-in self test; large scale integration; system-on-chip; BIST circuit; LSI tester; SoC; analog portion; deep sub-micron CMOS; production testing; system on chip; Built-in self-test; CMOS analog integrated circuits; Circuit testing; Costs; Electronic equipment testing; Large scale integration; Production; Semiconductor device testing; System testing; Wire;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1465577
