DocumentCode :
3547223
Title :
A two-step DDEM ADC for accurate and cost-effective DAC testing
Author :
Xing, Hanqing ; Chen, Degang ; Geiger, Randall
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
fYear :
2005
fDate :
23-26 May 2005
Firstpage :
4289
Abstract :
This paper presents a scheme for testing DAC static nonlinearity errors by using a two-step flash ADC with deterministic dynamic element matching (DDEM). In this work, the structure of the two-step ADC, the switching strategy of DDEM, and the DAC test algorithm are discussed. The performance of the proposed approach is validated by using numerical simulation. Simulation results show that a low accuracy two-step ADC with an 8-bit coarse stage and a 6-bit fine stage is capable of testing a 14-bit DAC to 1-LSB accuracy by using the proposed DDEM strategy. This test approach has potential for built-in self-test (BIST) of precision DAC because of the low requirement on ADC performance and the simple element matching strategy.
Keywords :
analogue-digital conversion; built-in self test; digital-analogue conversion; integrated circuit testing; mixed analogue-digital integrated circuits; 1-LSB accuracy; 14-bit DAC; 6-bit fine stage; 8-bit coarse stage; BIST; DAC testing; built-in self-test; deterministic dynamic element matching; static nonlinearity errors; two-step DDEM ADC; two-step flash ADC; Automatic testing; Built-in self-test; Computer errors; Digital-analog conversion; Integrated circuit technology; Mixed analog digital integrated circuits; Numerical simulation; Semiconductor device measurement; Signal generators; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
Type :
conf
DOI :
10.1109/ISCAS.2005.1465579
Filename :
1465579
Link To Document :
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