Optimal 2 sub-bank memory architecture for bit plane coder of JPEG2000

The JPEG2000 image compression standard is designed to cater for the needs of a large span of applications, including numerous consumer products. However, its use is still restricted due to its high computational and memory intensive nature. The bit plane coder (BPC) is one of the main resource intensive components of JPEG2000. Due to the unique memory access requirements of BPC, its memory controller and organisation contribute a high percentage of the overall hardware cost. We present an analysis of the BPC memory requirements and propose an optimal high speed 2 sub-bank based memory architecture. The overall architecture is implemented using Altera FPGA. The experimental results show savings of 77% in the hardware cost of the memory by keeping the memory requirement to its theoretical lower limit and using a very simple memory controller.