Architectures for ASIC implementations of low-density parity-check convolutional encoders and decoders

Author

Swamy, Ramkrishna ; Bates, Stephen ; Brandon, Tyler

Author_Institution

Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada

fYear

2005

fDate

23-26 May 2005

Firstpage

4513

Abstract

Low-density parity-check convolutional codes (LDPC-CCs) are an attractive alternative to their block-oriented counterparts, LDPC-BCs. In this paper, we introduce these codes and propose an encoder and decoder architecture that is implementable as an ASIC. We report upon a realization of this new architecture capable of an information throughput of 430 Mbps and 164 Mbps for the encoder and decoder, respectively. We discuss a top-level chip specification and then extend ideas to parallelize the design.

Keywords

application specific integrated circuits; convolutional codes; decoding; parity check codes; pipeline processing; 164 Mbit/s; 430 Mbit/s; ASIC implementation; LDPC-CC; decoders; encoders; information throughput; low-density parity-check convolutional codes; parallel architecture; pipelined encoder; Application specific integrated circuits; Block codes; CMOS technology; Computer architecture; Convolutional codes; Encoding; Field programmable gate arrays; Iterative decoding; Parity check codes; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465635

Filename

1465635