Title :
Performance-driven optimization for video accelerator design [video coding]
Author :
Lu, Yan-Chen ; Shen, Chun-Fu ; Chen, Chi-Kuang ; Fann, Ju-Lung
Author_Institution :
Vivotek Inc., Taipei, Taiwan
Abstract :
This paper presents a bandwidth-reduction oriented optimization for video encoding upon a platform-based architecture. We develop a bit-true C simulation model to estimate the system performance as well as to accelerate the HW design time and shorten the simulation/verification iteration. Its customized architecture can provide a solid evaluation before a real design is undertaken. The proposed accelerator contains two major modules which are designed by optimizing in bandwidth cost and application usage. The first one is a motion engine which takes charge of motion detection and estimation. The other module is a block engine which is well scheduled in block-based data flow and supports multi-standard (JPEG, H.263 and MPEG-4 SP) encoding. A novel data alignment method in frame memory reduces the bus bandwidth to 30% of the original. We verify our design in a 120 MHz AMBA platform and prove the capability of 30 fps VGA size encoding.
Keywords :
circuit optimisation; motion estimation; video coding; 120 MHz; FPGA; H.263; JPEG; MPEG-4 SP; VGA size encoding; application usage optimization; bandwidth cost optimization; bit-true C simulation model; block-based data flow; bus bandwidth-reduction; frame memory data alignment method; hardware accelerator; motion detection engine; motion estimation engine; multistandard encoding; video accelerator performance-driven optimization; well-scheduled pipeline architecture; Acceleration; Bandwidth; Cost function; Design optimization; Encoding; Engines; Motion detection; Solids; System performance; Video coding;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1465637
