A two-way SIMD-based reconfigurable computing architecture for multimedia applications

In this paper, a novel reconfigurable computing architecture for multimedia applications is proposed. The reconfigurable computing system comprises an ARM processor as the host CPU and the proposed reconfigurable computing engine to accelerate the operations of the multimedia algorithms. The proposed reconfigurable computing engine is composed of the SIMD-based function units, flexible interconnection networks, and two-bank on-chip memories. The SIMD-based function unit not only can perform 64-bit scalar operations but also can execute 8-bit, 16-bit, 32-bit SIMD instruction sets to increase the parallelism of the multimedia algorithms. In order to connect the function units, the reconfigurable network is proposed to connect all neighbors of each function unit. Owing to the above features, multimedia applications can be performed efficiently on the proposed reconfigurable architecture with high throughput.