DocumentCode
3547456
Title
An efficient architecture for the AES mix columns operation
Author
Li, Hua ; Friggstad, Zac
Author_Institution
Dept. of Math. & Comput. Sci., Lethbridge Univ., Alta., Canada
fYear
2005
fDate
23-26 May 2005
Firstpage
4637
Abstract
In this paper, a compact architecture for the AES mix columns operation and its inverse is presented. The hardware implementation is compared with previous work done in this area. We show that our design has a lower gate count than other designs that implement both the forward and the inverse mix columns operation.
Keywords
Galois fields; cryptography; matrix multiplication; AES mix columns operation; Galois fields; advanced encryption standard; inverse mix columns operation; low gate count hardware implementation; matrix multiplication; Computer architecture; Computer science; Cryptography; Delay; Galois fields; Hardware; Mathematics; Polynomials; Signal design; Wire; AES; Galois field; cryptography; mix columns;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1465666
Filename
1465666
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