A low-power and high-speed quaternary interconnection link using efficient converters

Author

Philippe, Jean-Marc ; Pillement, Sébastien ; Sentieys, Olivier

Author_Institution

IRISA, Univ. of Rennes 1, Lannion, France

fYear

2005

fDate

23-26 May 2005

Firstpage

4689

Abstract

We introduce a new quaternary link including a binary to-quaternary encoder and a quaternary-to-binary decoder in voltage-mode multiple-valued logic (MVL). This link improves the transistor count compared to existing designs and it has no DC current path. The complete link was simulated with SPICE in two recent technologies. It additionally shows interesting advantages in power consumption for global interconnects compared to full-swing signaling binary systems (up to 46% less energy consumption). Its low propagation delay is also an advantage in the design of high-speed on-chip links.

Keywords

code convertors; integrated circuit interconnections; low-power electronics; multivalued logic circuits; MVL; binary to-quaternary encoder; global interconnect power consumption reduction; high-speed quaternary interconnection link; low propagation delay interconnects; low-power interconnection link; on-chip links; quaternary-to-binary converters; quaternary-to-binary decoder; voltage mode converters; voltage-mode multiple-valued logic; Bandwidth; CMOS technology; Decoding; Energy consumption; Integrated circuit interconnections; Logic; Power system interconnection; Pulse modulation; Voltage; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465679

Filename

1465679