Analysis of power consumption in VLSI global interconnects

The analysis of effects induced by interconnects become increasingly important as the scale of process technologies steadily shrinks. While most analyses focus on the timing aspects of interconnects, power consumption is also important. We study the trends of interconnect power consumption based on current and future technology node parameters. We show that 20%-30% of the power is consumed by interconnect resistance in optimally buffered global interconnect systems. We also study the analysis method based on a reduced-order model. The relation between power consumption and the poles and residues of a transfer function is addressed. The theoretical results can be used for any kind of linear circuit, including RLC circuits.