Synthesis for regularity using decision diagrams [logic IC synthesis and layout]

Presented are new algorithms for synthesizing Boolean functions as regular logic structures. These regular structures can be mapped directly (without place&route) to a standard-cell library designed for regularity or to locally-connected programmable devices. The advantage of regular structures is that for a planar embedding the number of nodes in the expansion level grows at most linearly with the number of expansion variables. Regularity offers a predictable solution to hard problems arising in layout, at no extra cost or at the cost of increasing the number of gates, but without necessarily increasing circuit area. Increasing the number of logic levels does not translate into an increase in overall circuit delay, because regular, neighbor-to-neighbor connections reduce the wire delay, the dominant factor in deep sub-micron technology. This paper proposes new techniques which lead to less variable repetition and significantly improve the performance of synthesis algorithms. Experimental results much better than previously published data are very encouraging.