A cost-effective histogram test-based algorithm for digital calibration of high-precision pipelined ADCs

This work presents a self-calibration algorithm that corrects the linearity errors of pipelined ADC with a sub-radix architecture, based on the results of simple code density tests. The proposed algorithm identifies discontinuities in an ADC´s output histogram data, calculates correction codes for transitions in pipeline stages, and digitally calibrates ADC output codes. Simulation results show that the calibration algorithm can dramatically improve the linearity performance of ADC. The INL can be reduced from about 1000 LSB to less than 1 LSB. Since this algorithm is based on conventional code density tests and uses only a few memory cells and simple logic circuits to carry out the calibration, this algorithm can be easily implemented on chip without introducing much area and cost overhead and serving as a self-calibration solution for high-speed high-precision pipelined ADC.