A complete spurs distribution model for direct digital period synthesizers

This paper presents a new, fully automated algorithm modeling the spurious frequencies in direct digital period synthesizers (DDPS). DDPS is a frequency synthesis technique that combines the speed and low jitter of a delay-locked-loop-based frequency multiplier, with the ability to digitally control the frequency. The algorithm is based on an analysis of the periodicity of the output signal produced by a DDPS circuit on which a time-domain Fourier analysis is performed. The resulting spectrum reflects two major known sources of spurious frequencies in DDPS: accumulator output truncation and delay line cell mismatch. Comparisons with results obtained from time-consuming simulations performed with SIMULINK and processed by FFT were performed to validate the model. An efficient implementation of the proposed algorithm allows comparing many different operating conditions that could not be analyzed with the SIMULINK model due to excessive processing time.