DocumentCode
3547519
Title
Fully-differential 13 Gbps clock recovery circuit for OC-255 SONET applications
Author
Ho, Wen Tsern ; El-Gamal, Mourad N.
Author_Institution
Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, Que., Canada
fYear
2005
fDate
23-26 May 2005
Firstpage
4879
Abstract
A fully differential, quasi-mixer based, half-rate clock recovery PLL has been implemented in a 0.18-μm CMOS technology, and is optimized for high-speed of operation at 13 Gbit/s. A special differential varactor tuning arrangement is used to provide a wide operating frequency range from 6.2 GHz to 7.2 GHz, with a power consumption of 69 mW.
Keywords
CMOS integrated circuits; SONET; mixers (circuits); phase locked loops; synchronisation; varactors; 0.18 micron; 13 Gbit/s; 6.2 to 7.2 GHz; 69 mW; CMOS technology; OC-255 SONET applications; differential varactor tuning; fully differential PLL; half-rate clock recovery PLL; quasi-mixer based PLL; Charge pumps; Circuits; Clocks; Detectors; Filters; Frequency; Phase detection; SONET; Voltage; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1465726
Filename
1465726
Link To Document