Title :
A delay compensation technique for n-phase clock generation with 2(N-1) delay units
Author :
Chen, Xu ; Liu, Jin
Author_Institution :
Dept. of Electr. Eng., Texas Univ., Richardson, TX, USA
Abstract :
A new delay compensation technique based on phase interpolation is presented for the design of a multiphase clock generator. It reduces the number of delay units from n(n+1)/2 in prior art to 2(n-1) for an n-phase clock generator, thus greatly reducing the required die area and power consumption. Simulation of an eight-phase clock generator in 0.18-μm CMOS technology shows that the resulted multiphase clocks are precisely spaced when the delay of delay units varies from -15% to +25%.
Keywords :
CMOS integrated circuits; clocks; delay circuits; interpolation; power consumption; 0.18 micron; CMOS technology; delay compensation; delay units; die area; eight-phase clock generator; multiphase clock generator; n-phase clock generation; phase interpolation; power consumption; CMOS technology; Clocks; Delay effects; Delay lines; Energy consumption; Interpolation; Phase locked loops; Power generation; Signal generators; Space technology;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1465728
