A 53.3 Mb/s 4×4 16-QAM MIMO decoder in 0.35-μm CMOS

Author

Guo, Zhan ; Nilsson, Per-Ake

Author_Institution

Dept. of Electroscience, Lund Univ., Sweden

fYear

2005

fDate

23-26 May 2005

Firstpage

4947

Abstract

An ASIC implementation of the K-best Schnorr-Euchner decoder is presented for a 4×4 16-QAM MIMO system. There are several low complexity and low power features incorporated in the proposed VLSI architecture. The chip is fabricated in a 0.35-μm CMOS technology. The chip core area is 5.76 mm² with 91 K gates. Furthermore, the decoding throughput that the chip can support is up to 53.3 Mb/s with a core power consumption of 626 mW at 100 MHz clock frequency and 2.8 V supply. The corresponding decoding latency is 2.4 μs.

Keywords

CMOS digital integrated circuits; MIMO systems; VLSI; application specific integrated circuits; computational complexity; decoding; integrated circuit design; power consumption; quadrature amplitude modulation; radio links; 0.35 micron; 100 MHz; 16-QAM MIMO decoder; 2.4 mus; 2.8 V; 53.3 Mbit/s; 626 mW; ASIC; CMOS technology; K-best Schnorr-Euchner decoder algorithm; VLSI architecture; core power consumption; wireless communications; Application specific integrated circuits; CMOS technology; Clocks; Decoding; Delay; Energy consumption; Frequency; MIMO; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465743

Filename

1465743